The ability of quantum hardware to outperform classical hardware for tasks like computation, communication, and sensing is known as quantum advantage. Quantum advantage promises society-changing benefits including fundamentally secure communication, improved biomedical sensing, and breakthroughs in material and drug design. To date, useful quantum advantage for computation has not been realized. Though there is reason to be optimistic for near term advances, it is widely accepted that useful quantum advantage in computing will require fault tolerance at scale – an advance that is still beyond the reach of current devices.

This project is aiming to accelerate the development of fault-tolerant quantum computation by codesigning error correcting codes and the hardware that will run them. Currently, many quantum error correcting (QEC) codes have been discovered, and their mathematical structures are becoming better understood. Meanwhile, hardware with a few logical qubits has been demonstrated and, in some cases, a small gain in process fidelity realized. However, the demands on hardware for current QEC codes are severe – either enormous numbers of qubits are required or native gate fidelities must be extremely high (often, both). By designing QEC codes to utilize the native gates and connectivity of the hardware, while simultaneously optimizing the hardware layout to support the QEC code, fault tolerance can be achieved with the minimum resource cost thereby delivering useful quantum advantage sooner.